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d a t a sh eet product speci?cation 2002 may 28 integrated circuits SAA4979h sample rate converter with embedded high quality dynamic noise reduction and expansion port
2002 may 28 2 philips semiconductors product speci?cation sample rate converter with embedded high quality dynamic noise reduction and expansion port SAA4979h contents 1 features 2 general description 3 quick reference data 4 ordering information 5 block diagram 6 pinning 7 functional description 7.1 digital processing at 1f h level 7.1.1 itu 656 decoder 7.1.2 double window and picture-in-picture processing 7.1.3 black bar detector 7.1.4 dynamic noise reduction 7.1.5 noise estimator 7.2 embedded dram 7.2.1 3.5-mbit field memory 7.3 digital processing at 2f h level 7.3.1 sample rate conversion 7.3.2 expansion port 7.3.3 panoramic zoom 7.3.4 digital colour transient improvement 7.3.5 y horizontal smart peaking 7.3.6 non-linear phase filter 7.3.7 post processing 7.4 triple 10-bit digital-to-analog conversion 7.5 microcontroller 7.5.1 host interface 7.5.2 i 2 c-bus interface 7.5.3 snert-bus 7.5.4 i/o ports 7.5.5 watchdog timer 7.5.6 reset 7.6 system controller 7.6.1 read enable output 7.6.2 read enable input 7.6.3 input enable 7.6.4 horizontal deflection 7.6.5 vertical deflection 7.6.6 auxiliary display signal 7.6.7 read enable 2 7.6.8 output input enable 2 7.6.9 reset read 2 7.6.10 reset write 2 7.7 line-locked clock generation 7.8 boundary scan test 8 control register description 8.1 host interface detail 8.2 special function registers (sfrs) 9 limiting values 10 thermal characteristics 11 characteristics 12 transfer functions 13 application information 14 package outline 15 soldering 15.1 introduction to soldering surface mount packages 15.2 reflow soldering 15.3 wave soldering 15.4 manual soldering 15.5 suitability of surface mount ic packages for wave and reflow soldering methods 16 data sheet status 17 definitions 18 disclaimers 19 purchase of philips i 2 c components
2002 may 28 3 philips semiconductors product speci?cation sample rate converter with embedded high quality dynamic noise reduction and expansion port SAA4979h 1 features digital yuv input according to itu 656 standard 4:2:2 field rate upconversion (50 to 100 hz or 60 to 120 hz) 3.5-mbit embedded dram sample rate conversion for linear zoom and compression panorama mode dynamic noise reduction noise estimator black bar detection luminance horizontal smart peaking digital colour transient improvement (dcti) triple 10-bit digital-to-analog converter (dac) line-locked pll expansion port for saa4992h and saa4991wp double window and picture-in-picture (pip) processing embedded 80c51 microcontroller 32-kbyte internal rom (mask programmable) 512-byte internal ram i 2 c-bus controlled synchronous no parity eight bit reception and transmission (snert) interface boundary scan test (bst). 2 general description the SAA4979h provides an economic stand-alone solution for 4:2:2 field rate upconversion (50 to 100 hz or 60 to 120 hz) including the required field memory combined with picture improvement features and dynamic field based noise reduction. the ic contains two digital input channels to allow field or frame based picture-in-picture processing. it also offers a feature expansion port for vector based motion estimation and compensation ics such as saa4991wp or saa4992h. 3 quick reference data 4 ordering information symbol parameter min. typ. max. unit v ddd digital supply voltage 3.0 3.3 3.6 v v dda analog supply voltage 3.15 3.30 3.45 v v ddo ; v ddi i/o supply voltage 3.0 3.3 3.6 v v ddp protection supply voltage 3.0 5.0 5.5 v i ddd digital supply current - 120 160 ma i dda analog supply current - 40 50 ma p tot total power dissipation -- 0.9 w t amb ambient temperature - 20 - +70 c type number package name description version SAA4979h qfp128 plastic quad ?at package; 128 leads (lead length 1.6 mm); body 28 28 3.4 mm; high stand-off height sot320-2
2002 may 28 4 philips semiconductors product speci?cation sample rate converter with embedded high quality dynamic noise reduction and expansion port SAA4979h 5 block diagram handbook, full pagewidth mhc186 16 16 16 2 8 8 16 16 8 y [ 7:0 ] 10 i 2 c-bus tdo trst tms tck tdi bce yi7 to yi0 uvi7 to uvi0 yo7 to yo0 uvo7 to uvo0 boundary scan test panoramic zoom source select sample rate conversion 27 to 32 mhz pll rom i/o port snert- bus system controller microcontroller ram field memory 3.5 mbit dynamic noise reduction black bar detector noise estimator fast switch SAA4979h h h, v h, v clk32 sda, scl yout uout vout snda,sncl p1.2 to p1.5 snrst rei, rstw2 re2, rstr2 reo, ie, oie2 hd, vd, ads osco osci ext_clk di17 to di10 di27 to di20 llc2 llc1 clk32 rst href clk27 itu 656 decoder 1 source select main channel itu 656 decoder 2 sub channel upsampling bypass bypass downsampling uv upsampling 4 : 2 : 2 to 4 : 4 : 4 10 post processing blanking framing side panel triple 10-bit dac dcti chrominance circuit 10 y 2 non-linear phase filter horizontal smart y peaking luminance circuit fig.1 block diagram.
2002 may 28 5 philips semiconductors product speci?cation sample rate converter with embedded high quality dynamic noise reduction and expansion port SAA4979h 6 pinning symbol pin type description v ddo1 1 supply i/o supply voltage 1 (3.3 v) rstr2 2 digital output (test input) reset read, source 2 re2 3 digital output (test input) read enable, source 2 oie2 4 digital output (test input) output/input enable, source 2 v sso1 5 ground i/o ground 1 rstw2 6 digital input reset write, source 2 di10 7 digital input itu 656 input bit 0 (lsb), source 1 di11 8 digital input itu 656 input bit 1, source 1 di12 9 digital input itu 656 input bit 2, source 1 di13 10 digital input itu 656 input bit 3, source 1 di14 11 digital input itu 656 input bit 4, source 1 di15 12 digital input itu 656 input bit 5, source 1 di16 13 digital input itu 656 input bit 6, source 1 di17 14 digital input itu 656 input bit 7 (msb), source 1 v ssd1 15 ground digital ground 1 llc1 16 digital input 27 mhz clock signal, source 1 v ddd1 17 supply digital supply voltage 1 (3.3 v) v ddp 18 supply protection supply voltage (5 v) di20 19 digital input itu 656 input bit 0 (lsb), source 2 di21 20 digital input itu 656 input bit 1, source 2 di22 21 digital input itu 656 input bit 2, source 2 di23 22 digital input itu 656 input bit 3, source 2 di24 23 digital input itu 656 input bit 4, source 2 di25 24 digital input itu 656 input bit 5, source 2 di26 25 digital input itu 656 input bit 6, source 2 di27 26 digital input itu 656 input bit 7 (msb), source 2 v ssd2 27 ground digital ground 2 llc2 28 digital input 27 mhz clock signal, source 2 v ddd2 29 supply digital supply voltage 2 (3.3 v) tck 30 digital input test clock tdi 31 digital input test data input tms 32 digital input test mode select trst 33 digital input test reset (active low) n.c. 34 to 41 - not connected tdo 42 digital output test data output v dda1 43 supply analog supply voltage 1 (3.3 v) yout 44 analog output y analog output v ssa1 45 ground analog ground 1 uout 46 analog output - (b - y) analog output v dda2 47 supply analog supply voltage 2 (3.3 v)
2002 may 28 6 philips semiconductors product speci?cation sample rate converter with embedded high quality dynamic noise reduction and expansion port SAA4979h vout 48 analog output - (r - y) analog output v ssa2 49 ground analog ground 2 agnd 50 ground analog ground (without substrate contacts) bgext 51 analog i/o band gap external i/o v dda3 52 supply analog supply voltage 3 (3.3 v) v sso2 53 ground i/o ground 2 hd 54 digital output horizontal synchronisation output, display part vd 55 digital output vertical synchronisation output, display part v ssa3 56 ground analog ground 3 v ddi 57 supply i/o internal supply voltage (3.3 v) osci 58 analog input oscillator input osco 59 analog output oscillator output clkext 60 digital input external clock input v ddd3 61 supply digital supply voltage 3 (3.3 v) clk32 62 digital output 32 mhz clock output v ssd3 63 ground digital ground 3 v ddo2 64 supply i/o supply voltage 2 (3.3 v) uvi0 65 digital input uv digital input bit 0 (lsb) uvi1 66 digital input uv digital input bit 1 uvi2 67 digital input uv digital input bit 2 uvi3 68 digital input uv digital input bit 3 uvi4 69 digital input uv digital input bit 4 uvi5 70 digital input uv digital input bit 5 uvi6 71 digital input uv digital input bit 6 uvi7 72 digital input uv digital input bit 7 (msb) yi0 73 digital input y digital input bit 0 (lsb) yi1 74 digital input y digital input bit 1 yi2 75 digital input y digital input bit 2 yi3 76 digital input y digital input bit 3 yi4 77 digital input y digital input bit 4 yi5 78 digital input y digital input bit 5 yi6 79 digital input y digital input bit 6 yi7 80 digital input y digital input bit 7 (msb) rei 81 digital input read enable input v sso3 82 ground i/o ground 3 ie 83 digital output input enable reo 84 digital output read enable output yo7 85 digital output y digital output bit 7 (msb) yo6 86 digital output y digital output bit 6 yo5 87 digital output y digital output bit 5 yo4 88 digital output y digital output bit 4 symbol pin type description
2002 may 28 7 philips semiconductors product speci?cation sample rate converter with embedded high quality dynamic noise reduction and expansion port SAA4979h v ddo3 89 supply i/o supply voltage 3 (3.3 v) yo3 90 digital output y digital output bit 3 yo2 91 digital output y digital output bit 2 yo1 92 digital output y digital output bit 1 yo0 93 digital output y digital output bit 0 (lsb) v sso4 94 ground i/o ground 4 uvo7 95 digital output uv digital output bit 7 (msb) uvo6 96 digital output uv digital output bit 6 uvo5 97 digital output uv digital output bit 5 uvo4 98 digital output uv digital output bit 4 v ddo4 99 supply i/o supply voltage 4 (3.3 v) uvo3 100 digital output uv digital output bit 3 uvo2 101 digital output uv digital output bit 2 uvo1 102 digital output uv digital output bit 1 uvo0 103 digital output uv digital output bit 0 (lsb) v ssd4 104 ground digital ground 4 v ddd4 105 supply digital supply voltage 4 (3.3 v) ads 106 digital output auxiliary display signal sncl 107 digital output snert clock snda 108 digital i/o snert serial data v sso5 109 ground microcontroller i/o ground snrst 110 digital i/o snert restart (port 1.0) sda 111 digital i/o i 2 c-bus serial data (port 1.7) scl 112 digital i/o i 2 c-bus clock (port 1.6) p1.5 113 digital i/o port 1 data input/output signal 5 p1.4 114 digital i/o port 1 data input/output signal 4 p1.3 115 digital i/o port 1 data input/output signal 3 p1.2 116 digital i/o port 1 data input/output signal 2 v ddo5 117 supply microcontroller i/o supply voltage (3.3 v) rst 118 digital input microcontroller reset input n.c. 119 to 127 - not connected bce 128 digital input boundary scan compliant enable symbol pin type description
2002 may 28 8 philips semiconductors product speci?cation sample rate converter with embedded high quality dynamic noise reduction and expansion port SAA4979h handbook, full pagewidth mhc200 SAA4979h 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 yi7 yi6 yi5 yi4 yi3 yi2 yi1 yi0 uvi7 uvi6 uvi5 uvi4 uvi3 uvi2 uvi1 uvi0 uvo6 uvo7 v sso4 yo0 yo1 yo2 yo3 v ddo3 yo4 yo5 yo6 yo7 reo ie v sso3 rei v ddd1 v ddp di20 di21 di22 di23 di24 di25 di26 di27 v ssd2 llc2 v ddd2 tck tdi tms v ddo1 rstr2 re2 oie2 v sso1 rstw2 di10 di11 di12 di13 di14 di15 di16 di17 v ssd1 llc1 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 trst n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. tdo v dda1 yout v ssa1 uout v dda2 vout v ssa2 agnd bgext v dda3 v sso2 hd vd v ssa3 v ddi osci osco clkext v ddd3 clk32 v ssd3 v ddo2 bce n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. rst v ddo5 p1.2 p1.3 p1.4 p1.5 scl sda snrst v sso5 snda sncl ads v ddd4 v ssd4 uvo0 uvo1 uvo2 uvo3 v ddo4 uvo4 uvo5 fig.2 pin configuration.
2002 may 28 9 philips semiconductors product speci?cation sample rate converter with embedded high quality dynamic noise reduction and expansion port SAA4979h 7 functional description 7.1 digital processing at 1f h level 7.1.1 itu 656 decoder the SAA4979h provides 2 digital video input channels, which comply to the itu 656 standard. 720 active video pixels per line are processed at a line-locked clock of 27 mhz, which has to be provided by the signal source. luminance and chrominance information have to be multiplexed in the following order: c b1 ,y 1 ,c r1 ,y 2 , ... timing reference codes must be inserted at the beginning and end of each video line (see table 1): a start of active video (sav) code before the first active video sample (see table 2) a end of active video (eav) code after the last active video sample (see table 2). the incoming active video data must be limited to 1 to 254, since the data words 00h and ffh are used for identification of the timing reference headers. the digital signal input levels should comply to the ccir-601 standard (see fig.3). the data stream is decoded into the internal 4 :2:2 yuv format at a 13.5 mhz clock rate. if required the sign of the uv signals can be inverted for both channels (control inputs: uv_sign1 and uv_sign2). the signal source of the main channel can be selected from both inputs by the internal microcontroller (control input: select_data_input1). table 1 itu data format table 2 sav/eav format blanking period timing reference code (hex) 720 pixels yuv 4 :2:2 data timing reference code (hex) blanking period ... 80 10 ff 00 00 sav c b 0y0c r 0y1c b 2 y2 ... c r 718 y719 ff 00 00 eav 80 10 ... bit 7 bit 6 (f) bit 5 (v) bit 4 (h) bit 3 (p3) bit 2 (p2) bit 1 (p1) bit 0 (p0) 1 ?eld bit 1st ?eld: f = 0; 2nd ?eld: f = 1 vertical blanking bit vbi: v = 1; active video: v = 0 h = 0 in sav format; h = 1 in eav format reserved; evaluation not recommended (protection bits according to itu 656)
2002 may 28 10 philips semiconductors product speci?cation sample rate converter with embedded high quality dynamic noise reduction and expansion port SAA4979h handbook, full pagewidth luminance 100% + 255 + 235 + 128 + 16 0 white black u-component + 255 + 240 + 212 + 212 + 128 + 16 + 44 0 blue 100% blue 75% yellow 75% yellow 100% colourless v-component + 255 + 240 + 128 + 16 + 44 0 red 100% red 75% cyan 75% cyan 100% colourless mhc201 fig.3 digital video input levels. it should be noted that the input levels are limited to 1 to 254 in accordance with itu 601/656 standard. a. y output range. b. u output range (c b ). c. v output range (c r ). 7.1.2 d ouble window and picture - in - picture processing data from the sub channel can be inserted into the data stream of the main channel by means of a fast switch. the two channels can be used together with one or two external field memories to implement, for example, double window or pip processing. both field based and frame based pip processing is supported. the synchronization of the sub channel to the main channel is achieved by providing synchronized read signals (re2 and rstr2) for the external field memories, whereas the write signals need to be provided together with the incoming data by the external signal source. a multi-pip mode is also supported by freezing the data in the internal field memory within certain areas via the programmable internal control signal ie int . 7.1.3 b lack bar detector black bar detection searches for the last black line in the upper part of the screen and for the first black line in the lower part of the screen. the detection is done within a programmable window (control inputs: bbd_hstart, bbd_hstop, bbd_vstart and bbd_vstop). to avoid disturbances of logos in the video, the window can be shifted to the horizontal centre of the lines. a video line is considered to be black if the luminance values of that line within the detection window are not greater than a certain slice level (control input: bbd_slice_level) for more than a specific number of pixels (control input: bbd_event_value). the numbers of the first and the last active video line can be read out by the microcontroller (control outputs: bbd_1st_videoline and bbd_last_videoline).
2002 may 28 11 philips semiconductors product speci?cation sample rate converter with embedded high quality dynamic noise reduction and expansion port SAA4979h 7.1.4 d ynamic noise reduction the main function of the noise reduction is shown in fig.4. it is divided into two signal paths for chrominance and luminance. in principal two operating modes can be used, the fixed and the adaptive mode. in both modes the applied frequency range, in which the noise reduction takes place, can be reduced or not reduced (control input: unfiltered). the noise reduction operates field recursive with an averaging ratio (k factor) between fresh (new) and over previous fields averaged (old) luminance and chrominance values. noise reduction can be activated by forcing the nren control bit to high. if nren is low the noise reduction block is bridged via a data multiplexer. in the fixed mode, the noise reduction produces a constant weighted input averaging. because of smearing effects this mode should not be used for normal operation except for k = 1. the fixed mode can be activated separately for chrominance (control input: chromafix) and luminance (control input: lumafix). in the adaptive mode, the averaging ratio is based on the absolute differences of the inputs of luminance and chrominance respectively. if the absolute difference is low, only a small part of the fresh data will be added. in cases of high difference, much of the fresh data will be taken. this occurs either in situations of movement or where a significant vertical contrast is seen. the relationship between the amount of movement and the k factor values is defined in a look-up table where the steps can be programmed (control input: kstep). it should be noted that recursion is done over fields, and that pixel positions between the new and old fields always have a vertical offset of one line. so averaging is not only done in the dimension of time but also in the vertical direction. therefore averaging vertically on, for example, a vertical black to white edge would produce a grey result. the averaging in chrominance can optionally be slaved to the luminance averaging (control input: klumatochroma), in that case chrominance differences are not taken into account for the k factor setting of the chrominance signal path. the noise reduction scheme also decreases the cross-colour patterns effectively if the adaptive noise reduction for the averaging in chrominance is slaved to the luminance averaging (control input: klumatochroma). the cross-colour pattern does not produce an increase of the measured luminance difference, therefore this pattern will be averaged over many fields.
2002 may 28 12 philips semiconductors product speci?cation sample rate converter with embedded high quality dynamic noise reduction and expansion port SAA4979h handbook, full pagewidth dtomemory uv7 to uv0 data input uv7 to uv0 noise shape lut low-pass filter 2 8 control input: noiseshape control input: cadapt_gain control input: chromafix and klumatochroma control input: unfiltered processed uv kchroma kchromafix kluma uv average low-pass filter 1 abs/limiter hf delta u/v lf delta u/v new u/v 8 dfielddelay uv7 to uv0 8 old u/v delta u/v dtomemory y7 to y0 data input y7 to y0 noise shape lut low-pass filter 2 8 control input: noiseshape control input: yadapt_gain control input: lumafix control input: unfiltered processed y klumafix kluma low-pass filter 1 abs/limiter hf delta y lf delta y new y 8 dfielddelay y7 to y0 8 old y delta y mhc202 fig.4 schematic diagram of noise reduction.
2002 may 28 13 philips semiconductors product speci?cation sample rate converter with embedded high quality dynamic noise reduction and expansion port SAA4979h 7.1.4.1 band-splitting the frequencies of the difference signals of luminance (delta y) and chrominance (delta u/v) can be split optionally into an upper band (hf) and a lower band (lf) with a low-pass filter in both signal paths. the lower frequency band signals (lf delta y and lf delta u/v) are used as input for the noise reduction function. the lower frequency band of the difference signals can also be used for the motion detection. if, for example, only the lower frequency band contains information, the specific picture content does not move or is moving slowly. optionally it is possible to bridge the band-splitting (control input: unfiltered = 1). 7.1.4.2 motion detection the same signals (the noise reduction is applied to) are also used to detect the amount of motion in the difference signals. therefore, the absolute values of the difference signals are generated and limited to a maximum value. the absolute values of the difference signal of u and v are then averaged. the signals are low-pass filtered for smoothing these signals. the filtered signals are amplified, depending on the setting of the control inputs: yadapt_gain and cadapt_gain respectively. the amplified signals, which correlate to the amount of movement in the chrominance or luminance signal path, are transferred into 1 out of 9 possible k factor values via look-up tables. the look-up tables consist of 9 intervals, each related to one k factor. the boundaries between the 9 intervals are defined by 8 programmable steps (control inputs: kstep0 to kstep7). the step values are valid for the look-up tables for both the chrominance and the luminance path. for example, signal values between kstep2 and kstep3 result in a k factor of k = 3 / 8 . 7.1.4.3 k factor the amount of noise reduction (field averaging) is described my means of the k factor. when k = 1 no averaging is applied and the new field information is used. when k = 0 no averaging is applied and thus only the old field information is used like in a still picture mode. all values inbetween mean that a weighted averaging is applied. it is possible to use fixed k factor values if the control inputs lumafix or chromafix are set to logic 1. the possible fixed k factor values of the control inputs klumafix and kchromafix are given in table 6. 7.1.4.4 noise shape possible shadow picture information in the chrominance and luminance path, resulting from a low k factor value, will be eliminated if the noise shaping is activated. the noise shaping function can be switched off via the microcontroller (control input: noiseshape). 7.1.5 n oise estimator the noise level of the luminance signal can be measured within a programmable window (control inputs: ne_hstart, ne_hstop, ne_vstart and ne_vstop). the correlation in flat areas is used to estimate the noise in the video signal. a large number of estimates of the noise is calculated for every video field. such an estimate is obtained by summing absolute differences between current pixel values and delayed pixel values within blocks of 4 pixels. within the lower part of the total range of possible estimates 15 intervals are defined. each interval is defined by a lower boundary and an upper boundary. the lower boundary is equal to the number of the interval, whereas the upper boundary has a fixed relationship to the lower boundary (control input: gain_upbnd). the lower boundary is increased or decreased by 1 in each field until an interval is found which contains at least a predefined number of estimates, and is at the same time lowest in the range. the value of the lower boundary of this interval determines the current noise figure output. the predefined number of estimates can be set via the microcontroller (control input: wanted_value), and good results were obtained with a value which is approximately 0.27% of the total number of blocks. for video fields with a lot of noise the number of small differences is very low, that means the number of noise estimates in the lower intervals is close to 0. contrary to this, for clean sequences this number is very high. this means that for clean sequences the noise estimate figure will be close to 0, and for sequences with a lot of noise the noise estimate figure (control output: nest) will reach 15. to improve the performance of the noise estimator, several functions are implemented which can be controlled by the microcontroller. to increase the sensitivity of the noise measurement a prefilter with different gain settings is available (control input: ypscale). since the video content, e.g. sequences with a lot of high frequencies, can influence the noise estimate figure, a detail-counter is built-in.
2002 may 28 14 philips semiconductors product speci?cation sample rate converter with embedded high quality dynamic noise reduction and expansion port SAA4979h the detail-counter calculates the number of absolute differences between current and previous pixels within a programmable interval defined by the control inputs lb_detail and upb_detail. the result of the 16-bit detail-counter (control outputs: detail_cnt_h and detail_cnt_l) can be used to increase or decrease the result of the noise estimation figure (control input: compensate). in order to reduce the effect of clipping, only the blocks where the sum of the luminance value is within a predefined range are taken into account. the control signal clip_offs can be used to increase or decrease this range. a grey-counter gives information whether enough pixels with values in the grey range are present in a video field (control output: grey_cnt). when this number is lower than a predefined threshold, e.g. for complete fields towards black or white, all blocks are taken into account. 7.2 embedded dram 7.2.1 3.5-m bit field memory the basic functionality of the field memory, which is shown in fig.5, is similar to the saa4956tj. the memory size is extended to 3538944 bits. the data path is 16-bit wide (8-bit chrominance and 8-bit luminance). the field memory is capable of storing, for example, up to 307 video lines of 720 pixels in a 4:2:2 format. after writing or reading 18 words of 16-bit width, a data transfer is performed from the serial to parallel data registers (writing) or from the parallel to the serial registers (reading). the field memory has one write interface (controller and registers) to store 1f h data and two read interfaces, one to read field delayed 1f h data for the noise reduction function and the other to read 2f h data for the following data processing. since two asynchronous clock domains are involved (swckint as 1f h clock and srckint as 2f h clock) the read and write access to the memory array is controlled asynchronously by the memory arbitration logic triggered via request and acknowledge pulses. the write operation starts with a reset write (rstwint) address pointer operation during the write enable (weint) low phase. the rstwint low-to-high transition, referred to the rising edge of the write clock swckint, must be at least 18 clock cycles ahead of the first written data (weint high) and 18 clock cycles after the last written data. the reset write transfers data temporarily stored in the serial write registers to the memory array and resets the write counter to the lowest address. write enable (weint) is used to enable or disable a data write operation. the weint signal controls the data inputs d0 to d15. in addition, the internal write address pointer is incremented if weint is high at the positive transition of the swckint write clock. the data is latched if weint was high at the previous positive transition of swckint. input enable (ieint) low can also suppress the storage of the data into the memory array but does not influence the write pointer increment. it is used to freeze parts of the field data e.g for pip processing. the read operation starts with a reset (rstrint) of the read address pointer during the read enable (reint) low phase. the rstrint low-to-high transition, referred to the rising edge of the read clock srckint, must be at least 18 clock cycles ahead of the first read data (reint high) and 18 clock cycles after the last read data. the reset read resets the read counter to the lowest address and requests a read operation of the data of the lowest address to the serial read register. read enable (reint) is used to enable or disable the read operation. the reint controls the data outputs q0 to q15. reint high increments the read counter. in parallel to the write operation a read2 operation is done using the same control signals as the write operation: swckint, weint and rstwint. it reads the old data of the previous field. the data qold is needed as data input (dfielddelay) for the noise reduction. when the weint signal is high it indicates that active video (valid 1f h data) is to be stored. the start of weint high is triggered by the h and v status bits of the itu data stream. the start of weint high can be delayed by the control signals weint_hstart (number of clock delays) and weint_vstart (number of video lines delay). the stop of weint high is controlled by weint_hstop and weint_vstop. when the ieint signal is high it indicates that active video (valid 1f h data) is also to be stored. the video data is not stored and earlier written data is maintained (frozen) if weint is high and ieint is low. the start of ieint high is triggered by the h and v status bits of the itu data stream. the start of ieint high can be delayed by the control signals ieint_hstart (number of clock delays) and ieint_vstart (number of video lines delay). the stop of ieint high is controlled by ieint_hstop and ieint_vstop. rstwint is triggered by the v status bit of the itu data stream. rstrint is identical to the vd output signal. reint is provided by the following sample rate conversion to gather 2f h data if it is needed.
2002 may 28 15 philips semiconductors product speci?cation sample rate converter with embedded high quality dynamic noise reduction and expansion port SAA4979h handbook, full pagewidth mhc190 serial read2 controller weint rstwint swckint qold15 to qold0 q15 to q0 serial read controller reint rstrint srckint parallel read register 18-word ( 16) 18 16 parallel read2 register 18-word ( 16) memory array 221184-word ( 16) write address counter read2 address counter read address counter memory arbitration logic address and control 18 16 serial read register 18-word ( 16) 18 16 parallel write register 18-word ( 17) 18 (16 + 1) serial write register 18-word ( 17) serial write controller 18 (16 + 1) 17 d15 to d0 and ieint weint rstwint swckint serial read2 register 18-word ( 16) 18 16 16 16 read2 control (requests reset/next) read control (requests reset/next) read acknowledge read2 acknowledge write control (requests reset/next) fig.5 schematic diagram of 3.5-mbit field memory.
2002 may 28 16 philips semiconductors product speci?cation sample rate converter with embedded high quality dynamic noise reduction and expansion port SAA4979h 7.3 digital processing at 2f h level 7.3.1 s ample rate conversion the sample rate conversion block is used to obtain 848 active pixels per line out of the original 720 pixels according to the relation of the two sampling frequencies (32 mhz and 27 mhz). the interpolation for phase positions between the original samples is achieved with a variable phase delay filter with 10 taps for luminance signals and 6 taps for chrominance signals. the conversion to a higher sample frequency of 32 mhz is done to improve the motion estimation performance in combination with external feature ics, which can process up to 848 pixels per line at a 32 mhz clock. bypassing this function keeps the original 720 pixels per line (control input: bypass_fsrc). 7.3.2 e xpansion port for a further extension of the system an expansion port is available, which is applicable for either a 4:2:2 format or a reduced 4:1:1 format for data input and output at a 32 mhz line-locked clock; see table 3. however, the internal data is processed in a 8-bit wide 4 :2:2 format. to generate the 4:1:1 format at the output the u and v samples from the 4 : 2 : 2 data stream are filtered by a low-pass filter, before being subsampled with a factor of 2 and formatted to 4:1:1 format. bypassing this function keeps the data in the 4:2:2 format. an internal bandwidth detector is implemented to detect whether the colour difference signals provide either the full 4:2:2 bandwidth or a reduced 4 : 1 : 1 bandwidth. therefore absolute differences between original data and downsampled data are calculated and can be read out by the microcontroller (control output: uv_bw_detect). low absolute differences indicate that the original data does not contain the full 4:2:2 bandwidth. this information can be used to switch the upsample and downsample filter on or off (control inputs: bypass_upsampling and bypass_downsampling). bandwidth detection is done within a programmable window (control inputs: bw_hstart, bw_hstop and bw_vstart, bw_vstop). in the event of a 4 : 1 : 1 format at the input an upconverter to 4:2:2 is applied with a linear interpolation filter for creation of the extra samples. these are combined with the original samples from the 4 : 1 : 1 stream. the first phase of the yuv data stream is available on the output bus two clock cycles after the rising edge of the rei input signal. the start position, when the first phase of the yuv data stream arrives on the input bus, can be set via the control register exp_hstart. the luminance output signal is in 8-bit straight binary format, whereas the chrominance output signals are in twos complement format. the input data at the expansion slot is expected in the same format. u and v input signals are inverted if the corresponding control bit mid_uv_inv is set. table 3 yuv formats output pin 4:1:1 format 4:2:2 format input pin yo7 y07 y17 y27 y37 y07 y17 yi7 yo6 y06 y16 y26 y36 y06 y16 yi6 yo5 y05 y15 y25 y35 y05 y15 yi5 yo4 y04 y14 y24 y34 y04 y14 yi4 yo3 y03 y13 y23 y33 y03 y13 yi3 yo2 y02 y12 y22 y32 y02 y12 yi2 yo1 y01 y11 y21 y31 y01 y11 yi1 yo0 y00 y10 y20 y30 y00 y10 yi0 uvo7 u07 u05 u03 u01 u07 v07 uvi7 uvo6 u06 u04 u02 u00 u06 v06 uvi6 uvo5 v07 v05 v03 v01 u05 v05 uvi5 uvo4 v06 v04 v02 v00 u04 v04 uvi4 uvo3 ---- u03 v03 uvi3 uvo2 ---- u02 v02 uvi2 uvo1 ---- u01 v01 uvi1 uvo0 ---- u00 v00 uvi0
2002 may 28 17 philips semiconductors product speci?cation sample rate converter with embedded high quality dynamic noise reduction and expansion port SAA4979h 7.3.3 p anoramic zoom the panoramic zoom block contains a second sample rate converter, which performs the following tasks: linear horizontal sample rate conversion in both zoom and compress direction, with a sample rate conversion factor between 0 and 2, meaning infinite zoom up to a compression with a factor of 2 dynamic sample rate conversion e.g. for panorama mode display of 4 : 3 material on a 16 : 9 screen. for linear horizontal zoom or compression the sample rate conversion factor is static during a video line (control input: c0). positive values of c0 are suitable for compression, negative values result in expansion. in panorama mode the video lines are geometrically expanded towards the sides. the sample rate conversion factor is modulated along the video line. a parabolic shape of the sample rate conversion factor can be obtained with the parameter c2, which controls the second order variation of the sample rate. negative values of c2 are suitable for panorama mode, positive values result in the inverse mode (amaronap mode). the panoramic zoom block also provides a dynamically controlled delay with an accuracy up to 1 64 of a pixel and a range of - 0.5 to +0.5 lines (control input: hshift). sufficient accuracy in interpolation for phase positions between the original samples is achieved with a variable phase delay filter with 10 taps for luminance signals and 6 taps for chrominance signals. 7.3.4 d igital colour transient improvement the digital colour transient improvement (dcti) is intended for u and v signals originating from a 4:1:1 source. horizontal transients are detected and enhanced without overshoots by differentiating, make absolute and again differentiating the u and v signals separately. this results in a 4:4:4 uandv bandwidth. to prevent third-harmonic distortion, which is typical for this processing, a so called over the hill protection prevents peak signals becoming distorted. it is possible to control the following settings via the microcontroller: gain width (see fig.10), threshold (i.e. immunity against noise), selection of simple or improved first differentiating filter (see fig.9), limit for pixel shift range (see fig.11), common or separate processing of u and v signals, hill protection mode (i.e. no discolourations in narrow colour gaps), low-pass filtering for u and v signals (see fig.12) and a so called super hill mode, which avoids discolourations in transients within a colour component. 7.3.5 horizontal smart y peaking a linear peaking is applied, which amplifies the luminance signal in the middle and the upper ranges of the bandwidth. the filtering is an addition of: the original signal the original signal high-passed with maximum gain at a frequency of 1 2 f s (sample frequency f s = 32 mhz) the original signal band-passed with a centre frequency of 1 4 f s the original signal band-passed with a centre frequency of 4.76 mhz. the band-passed and high-passed signals are weighted with the factors 0, 1 16 , 2 16 , 3 16 , 4 16 , 5 16 , 6 16 and 8 16 , resulting in a maximum gain difference of 2 db per step at the centre frequencies. coring is added to avoid amplification of low amplitudes in the high-pass and band-pass filtered signals, which are considered to be noise. the coring threshold can be programmed as 0 (off), 4, 8, 12 to 60 lsb with respect to the (signed) 10-bit signal. in addition the peaking gain can be reduced depending on the signal amplitude, programming range 0 (no attenuation), 1 4 , 2 4 and 4 4 . it is also possible to make larger undershoots than overshoots, programming range 0 (no attenuation of undershoots), 1 4 , 2 4 and 4 4 . a steepness detector is built-in, which provides information for dynamic control of the peaking. for that the maximum absolute value of the band-pass filtered signal within a video field is calculated and can be read out by the microcontroller (control output: steepness_max). 7.3.6 n on - linear phase filter the non-linear phase filter adjusts possible group delay differences in the y, u and v output channels. the filter coefficients are: [ -l (1 -m ); 1 + l ; -lm ] where l determines the strength of the filter and m determines the asymmetry. the effect of the asymmetry is a decrease in the delay for higher frequencies with m 0.5. control settings are provided for l =0, 1 8 , 2 8 , 3 8 and m =0, 1 4 , 1 2 .
2002 may 28 18 philips semiconductors product speci?cation sample rate converter with embedded high quality dynamic noise reduction and expansion port SAA4979h 7.3.7 p ost processing blanking is done just before the digital-to-analog conversion by switching y to a fixed black value and uv to a colourless value. the blanking window is defined by the control inputs: bln_hstart, bln_hstop, bln_vstart and bln_vstop. side panels are generated by switching the y, u and v to defined values within a horizontal window (control inputs: sidepanel_hstart and sidepanel_hstop); the 8 msbs of y and the 4 msbs of u and v are programmable (control inputs: sidepanel_y, sidepanel_u and sidepanel_v). framing e.g. for picture-in-picture mode, can be achieved by another programmable window (control inputs: pip_frame_hstart, pip_frame_hstop, pip_frame_vstart and pip_frame_vstop). the vertical and horizontal frame width can be programmed from 1 up to 15 pixels (control inputs: pip_frame_heigth and pip_frame_width). framing uses the same colour and luminance values as the side panels. the range of the y output signal can be chosen between 9 and 10 bits (control input: output_range). in the event of 9 bits for the nominal signal there is room left for under and overshoot, adding up to a total of 10 bits. in the event of selecting all 10 bits of the luminance digital-to-analog converter for the nominal signal any under or overshoot will be clipped (see fig.6). the y samples can be shifted onto 16 positions with respect to the uv samples (control input: y_delay). the zero delay setting is suitable for the nominal case of aligned input data. the other settings provide eight samples with less delay to seven samples with more delay in y. 7.4 triple 10-bit digital-to-analog conversion three identical 10-bit converters are used to map the 4:4:4 yuv data to analog levels with a 32 mhz data rate. the polarity of the colour difference signals u and v is switchable by the control bit uv_inv_out. the output ranges are illustrated in figs 6 and 7 respectively. handbook, full pagewidth mhc191 0 (16) 288 1023 (235) 727 1.0 v (p-p) 1.0 v (p-p) (0) 0 (16) 64 v oy + 1.095 v v oy - 0.073 v v oy + 1.0 v v oy v oy + 1.674 v v oy - 0.656 v v oy + 1.0 v v oy (255) 1023 (235) 940 (255) 766 (0) 256 black white black white fig.6 luminance output levels. a. output range = 1. b. output range = 0.
2002 may 28 19 philips semiconductors product speci?cation sample rate converter with embedded high quality dynamic noise reduction and expansion port SAA4979h handbook, full pagewidth mhc192 (0) 0 (44) 176 (255) 1023 (212) 848 (128) 512 (0) 0 (44) 176 (255) 1023 (212) 848 (128) 512 1.33 v (p-p) 1.05 v (p-p) v ou + 1.012 v v ou - 1.012 v v ou + 0.665 v v ou - 0.665 v v ou v ov + 0.8 v v ov - 0.8 v v ov + 0.575 v v ov - 0.575 v v ov blue 75% yellow 75% colourless red 75% cyan 75% colourless fig.7 chrominance output levels. a. u output level. b. v output level. 7.5 microcontroller the SAA4979h contains an embedded 80c51 microcontroller core including 512-byte ram and 32-kbyte rom. the microcontroller runs on a 16 mhz clock, generated by dividing the 32 mhz display clock by a factor of 2. 7.5.1 h ost interface for controlling internal registers a host interface, consisting of a parallel address and data bus, is built-in. the interface can be addressed as internal auxram via a movx type of instruction. the complete range of internal control registers and the corresponding host addresses are described in section 8.1. user access to these control registers via the i 2 c-bus can be implemented in the embedded software. 7.5.2 i 2 c- bus interface the i 2 c-bus interface in the SAA4979h is used in a slave receive and transmit mode for communication with a central system microcontroller. the standardized bus frequencies of both 100 khz and 400 khz can be accommodated. the i 2 c-bus slave address of the SAA4979h is 0110100 r/ w. during slave transmit mode the scl low period may be extended by pulling scl to low (in accordance with the i 2 c-bus specification). detailed information about the software dependent i 2 c-bus subaddresses of the control registers and a detailed description of the transmission protocol can be found in application note i 2 c-bus register specification of the SAA4979h . 7.5.3 snert- bus interface a snert interface is built-in, which operates in a master receive and transmit mode for communication with peripheral circuits such as saa4991wp or saa4992h. the snert interface replaces the standard uart interface. contrary to the 80c51 uart interface there are additional special function registers (see table 10) and there is no byte separation time between address and data.
2002 may 28 20 philips semiconductors product speci?cation sample rate converter with embedded high quality dynamic noise reduction and expansion port SAA4979h the snert interface transforms the parallel data from the microcontroller into 1 or 2 mbaud snert data, switchable via microcontroller. the snert-bus consists of three signals: sncl used as serial clock signal, generated by the snert interface; snda used as bidirectional data line and snrst used as reset signal, generated by the microcontroller at port pin p1.0 to indicate the start of a transmission. the read or write operation must be set by the microcontroller. when writing to the bus, 2 bytes are loaded by the microcontroller: one for the address, the other for the data. when reading from the bus, one byte is loaded by the microcontroller for the address, the received byte is the data from the addressed snert location. 7.5.4 i/o ports a parallel 8-bit i/o port (p1) is available, where p1.0 is used as snert reset signal (snrst), p1.2 to p1.5 can be used for application specific control signals, and p1.6 and p1.7 are used as i 2 c-bus signals (scl and sda). 7.5.5 w atchdog timer the microcontroller contains an internal watchdog timer, which can be activated by setting the corresponding special function register pcon.4. only a synchronous reset will clear this bit. to prevent a system reset the watchdog timer must be reloaded within a specified time. the watchdog timer contains an 11-bit prescaler and is therefore incremented every 0.768 ms (16 mhz clock). the time interval between the timers reloading and the occurrence of a reset depends on the reloaded 8-bit value. 7.5.6 r eset a reset is accomplished by holding the rst pin high for at least 0.75 m s while the display clock is running and the supply voltage is stabilized. 7.6 system controller the system controller provides all necessary internal read and write signals for controlling the embedded field memory. the required control signals (reo and ie) for applications with motion compensation circuits and the drive signals (hd and vd) for the horizontal and vertical deflection power stages are also generated. the system controller also supports double window or picture-in-picture processing in combination with an external field memory by providing the required memory control signals (re2, rstw2 and oie2). the system controller is connected to the microcontroller via the host interface. 7.6.1 r ead enable output the read enable output (reo) signal is intended for control of an external feature ic. it is a composite signal consisting of a horizontal and a vertical part. the horizontal and vertical positions are programmable (control inputs: reo_hstart, reo_hstop, reo_vstart and reo_vstop). 7.6.2 r ead enable input the read enable input (rei) signal is used in applications with external feature ics connected to the expansion port. it has to be provided by the external circuit (see section 7.3.2). 7.6.3 i nput enable the input enable (ie) signal is intended for control of field memories in applications together with an external feature ic connected to the expansion port. it can be directly set or reset via the microcontroller. 7.6.4 h orizontal deflection the horizontal deflection (hd) signal is for driving a deflection circuit; start and stop values of the horizontal position are programmable in a resolution of 4 clock cycles (control inputs: hd_start and hd_stop). 7.6.5 v ertical deflection the vertical deflection (vd) signal is for driving a deflection circuit. this signal has a cycle time of 10 ms and the start and stop values of the vertical position are programmable in steps of 16 m s (control inputs: vd_start and vd_stop). 7.6.6 a uxiliary display signal the auxiliary display signal (ads) is for general purposes; the horizontal and vertical positions are programmable (control inputs: ads_hstart, ads_hstop, ads_vstart and ads_vstop). 7.6.7 r ead enable 2 the read enable 2 (re2) signal is intended for control of an external field memory at input channel 2 in picture-in-picture applications. it is a composite signal consisting of a horizontal and a vertical part. the horizontal and vertical positions are programmable (control inputs: re2_hstart, re2_hstop, re2_vstart and re2_vstop).
2002 may 28 21 philips semiconductors product speci?cation sample rate converter with embedded high quality dynamic noise reduction and expansion port SAA4979h 7.6.8 o utput /i nput enable 2 the output/input enable 2 (oie2) signal is intended for control of one or two external field memories at input channel 2 in picture-in-picture applications. it can be directly set or reset via the microcontroller. 7.6.9 r eset read 2 the reset read 2 (rstr2) signal is intended for control of the read access of an external field memory at input channel 2 in picture-in-picture applications. it is derived from the internal vertical reference signal of the main channel. 7.6.10 r eset write 2 the reset write 2 (rstw2) input is used in picture-in-picture applications with an external field memory at input channel 2, and has to be provided by an external circuit which controls the field memory write access. 7.7 line-locked clock generation an internal pll generates the 32 mhz line-locked display clock clk32. the pll consists of a ring oscillator, dto and digital control loop. the pll characteristic is controlled by means of the microcontroller. 7.8 boundary scan test the SAA4979h has built-in logic and 6 dedicated pins to support boundary scan testing which allows board testing without special hardware (nails). the SAA4979h follows the ieee std. 1149.1 - standard test access port and boundary-scan architecture set by the joint test action group (jtag) chaired by philips. the 6 special pins are test mode select (tms), test clock (tck), test reset ( trst), test data input (tdi), boundary-scan compliant enable (bce) and test data output (tdo). to achieve compliance to the ieee std. 1149.1 a logic high has to be applied to the bce pin. internal pull-up resistors at the input pins tms, trst and tdi are not implemented. 8 control register description 8.1 host interface detail table 4 write register at 1f h host address (hex) bit name description host address 0102h to 011ch (system control) 0102 0 to 7 weint_vstart write enable internal memory vertical start (lower 8 of 9 bits) 0103 0 to 7 weint_vstop write enable internal memory vertical stop (lower 8 of 9 bits) 0104 0 weint_vstart (msb) write enable internal memory vertical start (msb) 1 weint_vstop (msb) write enable internal memory vertical stop (msb) 2 fm1_still still picture mode; 0 = normal mode, 1 = still picture mode 3 pip_2fm_dc direct controlled pip mode; 0 = normal mode, 1 = direct mode 4 sfr ?eld recognition mode; 0 = normal mode, 1 = inverse mode 5 sfm single ?eld mode; 0 = normal mode, 1 = single ?eld mode 6 re2_vstart (msb) read enable pip window vertical start (msb) 7 re2_vstop (msb) read enable pip window vertical stop (msb) 0105 0 to 7 re2_vstart read enable pip window vertical start (lower 8 of 9 bits) 0106 0 to 7 re2_vstop read enable pip window vertical stop (lower 8 of 9 bits) 0107 0 to 7 re2_hstart read enable pip window horizontal start (lower 8 of 10 bits) 0108 0 to 7 re2_hstop read enable pip window horizontal stop (lower 8 of 10 bits)
2002 may 28 22 philips semiconductors product speci?cation sample rate converter with embedded high quality dynamic noise reduction and expansion port SAA4979h 0109 0 to 3 min_dist_maintosub minimum distance between main and sub channel 4 pip_raster_corr pip raster correction; 0 = off, 1 = on 5 pip_on pip mode; 0 = off, 1 = on 6 pip_2?eld pip 2-?eld mode; 0 = single ?eld mode, 1 = 2-?eld mode 7 mpip_on multi-pip mode; 0 = off, 1 = on 010a 0 to 7 dispvpos vertical position of the display related to acquisition 0112 0 to 7 weint_hstart write enable internal memory horizontal start (lower 8 of 10 bits) 0113 0 to 7 weint_hstop write enable internal memory horizontal stop (lower 8 of 10 bits) 0114 0 to 1 weint_hstart (msbs) write enable internal memory horizontal start (higher 2 of 10 bits) 2 to 3 weint_hstop (msbs) write enable internal memory horizontal stop (higher 2 of 10 bits) 4 to 5 re2_hstart (msbs) read enable pip window horizontal start (higher 2 of 10 bits) 6 to 7 re2_hstop (msbs) read enable pip window horizontal stop (higher 2 of 10 bits) 0116 0 to 7 h656int_hstart internal h reference horizontal start; 4 pixel resolution 0117 0 to 7 h656int_hstop internal h reference horizontal stop; 4 pixel resolution 0118 0 to 7 ieint_hstart input enable internal memory horizontal start (lower 8 of 10 bits) 0119 0 to 7 ieint_hstop input enable internal memory horizontal stop (lower 8 of 10 bits) 011a 0 to 7 ieint_vstart input enable internal memory vertical start (lower 8 of 10 bits) 011b 0 to 7 ieint_vstop input enable internal memory vertical stop (lower 8 of 10 bits) 011c 0 to 1 ieint_hstart (msbs) input enable internal memory horizontal start (higher 2 of 10 bits) 2 to 3 ieint_hstop (msbs) input enable internal memory horizontal stop (higher 2 of 10 bits) 4 ieint_vstart (msb) input enable internal memory vertical start (msb) 5 ieint_vstop (msb) input enable internal memory vertical stop (msb) 6to7 - reserved host address 0185h to 018eh (noise estimator) 0185 0 to 1 ypscale scale of pre?lter coef?cients: ( 1 1 , 1 2 , 1 4 , bypass pre?lter) 2 to 5 compensate compensation value (4-bit signed) 6to7 - reserved 0186 0 to 2 gain_upbnd gain of upper boundary: 0, 1, 2, 3, 4, 5, 6 and 7 3 sob_negl neglect sum over block value if high 4 sel_sob_negl enable of control bit sob_negl: 0 = disable, 1 = enable 5 to 6 clip_offs clip offset: 1, 2, 4 and 8 7 - reserved 0187 0 to 7 wanted_value wanted value in steps of 1 256 %, i.e. prede?ned number of estimates; range: 0 to 255 256 % 0188 0 to 7 lb_detail lower boundary of detail counter 0189 0 to 7 upb_detail upper boundary of detail counter 018a 0 to 7 ne_hstart noise measurement window horizontal start; 4 pixel resolution 018b 0 to 7 ne_hstop noise measurement window horizontal stop; 4 pixel resolution 018c 0 to 7 ne_vstart noise measurement window vertical start (lower 8 of 9 bits) host address (hex) bit name description
2002 may 28 23 philips semiconductors product speci?cation sample rate converter with embedded high quality dynamic noise reduction and expansion port SAA4979h 018d 0 to 7 ne_vstop noise measurement window vertical stop (lower 8 of 9 bits) 018e 0 ne_vstart (msb) noise measurement window vertical start (msb) 1 ne_vstop (msb) noise measurement window vertical stop (msb) 2to7 - reserved host address 018fh (front-end control) 018f 0 select_data_input1 select data input for main channel: 0 = input 2, 1 = input 1 1 uv_sign1 uv sign of main channel 1: 0 = unsigned, 1 = signed 2 uv_sign2 uv sign of sub channel 2: 0 = unsigned, 1 = signed 3to7 - reserved host address 0190h to 0196h (noise reduction) 0190 0 to 3 kstep0 step in adaptive curve from k = 1 16 to k = 1 8 ; weight of 1 4 to 7 kstep1 step in adaptive curve from k = 1 8 to k = 2 8 ; weight of 1 0191 0 to 3 kstep2 step in adaptive curve from k = 2 8 to k = 3 8 ; weight of 2 4 to 7 kstep3 step in adaptive curve from k = 3 8 to k = 4 8 ; weight of 2 0192 0 to 3 kstep4 step in adaptive curve from k = 4 8 to k = 5 8 ; weight of 4 4 to 7 kstep5 step in adaptive curve from k = 5 8 to k = 6 8 ; weight of 4 0193 0 to 3 kstep6 step in adaptive curve from k = 6 8 to k = 7 8 ; weight of 8 4 to 7 kstep7 step in adaptive curve from k = 7 8 to k = 8 8 ; weight of 8 0194 0 to 3 kluma?x value of the ?xed k factor of the luminance; see table 6 4 to 6 yadapt_gain value of the gain of the adaptive curve of the luminance; see table 5 7 luma?x adaptive (luma?x = 0) or ?xed k mode (luma?x = 1) of the luminance 0195 0 to 3 kchroma?x value of the ?xed k factor of the chrominance; see table 6 4 to 6 cadapt_gain value of the gain of the adaptive curve of the chrominance; see table 5 7 chroma?x adaptive (chroma?x = 0) or ?xed k mode (chroma?x = 1) of chrominance 0196 0 klumatochr if high: uses luminance k factor for chrominance path 1 un?ltered if high: band splitting is deactivated, complete difference signals are used 2 noiseshape if high: noise shaping is activated 3 splitscreen if high: split screen demo mode is activated 4 nren noise reduction enable; 0 = off; 1 = on 5to7 - reserved host address 019ah to 019fh (black bar detection) 019a 0 to 5 bbd_event_value black bar detection event value 6to7 - reserved 019b 0 to 5 bbd_slice_level black bar detection slice level 6 bbd_vstop (msb) black bar detection window vertical stop (msb) 7 bbd_vstart (msb) black bar detection window vertical start (msb) 019c 0 to 7 bbd_hstart black bar detection window horizontal start; 4 pixel resolution host address (hex) bit name description
2002 may 28 24 philips semiconductors product speci?cation sample rate converter with embedded high quality dynamic noise reduction and expansion port SAA4979h table 5 gain settings of adaptive values for chrominance and luminance table 6 settings of ?xed k factor values 019d 0 to 7 bbd_hstop black bar detection window horizontal stop; 4 pixel resolution 019e 0 to 7 bbd_vstart black bar detection window vertical start (lower 8 of 9 bits) 019f 0 to 7 bbd_vstop black bar detection window vertical stop (lower 8 of 9 bits) yadapt_gain/cadapt_gain [2:0] gain hex decimal 00 0 1 8 01 1 2 8 02 2 4 8 03 3 8 8 04 4 16 8 05 5 32 8 06 6 64 8 07 7 128 8 kluma?x/kchroma?x [3:0] k factor hex decimal 00 0 0 01 1 1 16 02 2 2 16 03 3 3 16 04 4 4 16 05 5 5 16 06 6 6 16 07 7 7 16 08 8 8 16 09 9 9 16 0a 10 10 16 0b 11 11 16 0c 12 12 16 0d 13 13 16 0e 14 14 16 0f 15 16 16 host address (hex) bit name description
2002 may 28 25 philips semiconductors product speci?cation sample rate converter with embedded high quality dynamic noise reduction and expansion port SAA4979h table 7 write register at 2f h host address (hex) bit name description host address 0222h to 023fh (system control) 0222 0 to 7 vd_vstart vertical de?ection pulse start (lower 8 of 11 bits) 0223 0 to 7 vd_vstop vertical de?ection pulse stop (lower 8 of 11 bits) 0224 0 to 7 reo_vstart read enable output window vertical start (lower 8 of 10 bits) 0225 0 to 7 reo_vstop read enable output window vertical stop (lower 8 of 10 bits) 0226 0 to 3 dsp?ds number of display ?elds minus 1 4to7 - reserved 0227 0 to 1 reo_vstart (msbs) read enable output window vertical start (higher 2 of 10 bits) 2 to 3 reo_vstop (msbs) read enable output window vertical stop (higher 2 of 10 bits) 4to7 - reserved 0228 0 to 2 vd_vstart (msbs) vertical de?ection pulse start (higher 3 of 11 bits) 3 to 4 vd_vstop (msbs) vertical de?ection pulse start (higher 3 of 11 bits) 6to7 - reserved 0229 0 to 7 ads_hstart auxiliary display signal horizontal start (lower 8 of 10 bits) 022a 0 to 7 ads_hstop auxiliary display signal horizontal stop (lower 8 of 10 bits) 022b 0 vres_dis internal vertical reset; 0 = enable; 1 = disable 1 crn_direct direct vertical frame synchronization; 0 = disable; 1 = enable 2 dr_aabb display raster mode; 0 = standard vd synchronization; 1 = aabb synchronization; vd delayed for the ?rst 50 hz ?eld 3 - reserved 4 gen_mode generator mode; 0 = off; 1 = on 5 ie_fm2 input enable signal (output ie) 6 smooth_lock smooth lock synchronization mode; 0 = off; 1 = on 7 - reserved 022c 0 to 7 ads_vstart auxiliary display signal vertical start (lower 8 of 10 bits) 022d 0 to 7 ads_vstop auxiliary display signal vertical stop (lower 8 of 10 bits) 022e 0 to 1 ads_hstart (msbs) auxiliary display signal horizontal start (higher 2 of 10 bits) 2 to 3 ads_hstop (msbs) auxiliary display signal horizontal stop (higher 2 of 10 bits) 4 to 5 ads_vstart (msbs) auxiliary display signal vertical start (higher 2 of 10 bits) 6 to 7 ads_vstop (msbs) auxiliary display signal vertical stop (higher 2 of 10 bits) 0230 0 to 7 hd_hstart horizontal de?ection pulse start; 4 pixels resolution 0231 0 to 7 hd_hstop horizontal de?ection pulse stop; 4 pixels resolution 0234 0 to 7 reo_hstart read enable output window horizontal start (lower 8 of 10 bits) 0235 0 to 7 reo_hstop read enable output window horizontal stop (lower 8 of 10 bits) 0238 0 to 1 reo_hstart (msbs) read enable output window horizontal start (higher 2 of 10 bits) 2 to 3 reo_hstop (msbs) read enable output window horizontal stop (higher 2 of 10 bits) 4to7 - reserved 023a 0 to 7 ? display ?eld length (lower 8 of 11 bits)
2002 may 28 26 philips semiconductors product speci?cation sample rate converter with embedded high quality dynamic noise reduction and expansion port SAA4979h 023b 0 to 2 ? (msbs) display ?eld length (higher 3 of 11 bits) 3to7 - reserved 023c 0 to 7 hp1 frame synchronization pulse position; 4 pixels resolution 023d 0 to 7 dsplock_vstart display locking window vertical start (lower 8 of 10 bits) 023e 0 to 7 dsplock_vstop display locking window vertical stop (lower 8 of 10 bits) 023f 0 to 1 dsplock_vstart (msbs) display locking window vertical start (higher 2 of 10 bits) 2 to 3 dsplock_vstop (msbs) display locking window vertical stop (higher 2 of 10 bits) 4to7 - reserved host address 0287h to 028dh (panoramic zoom) 0287 0 to 7 c2 compression or expansion non-linearity value 0288 0 to 7 c0 linear compression or expansion value (lower 8 of 9 bits) 0289 0 to 7 hshift (lsbs) horizontal pixel shift (lower 8 of 16 bits) 028a 0 to 7 hshift (msbs) horizontal pixel shift (higher 8 of 16 bits) 028b 0 to 7 nrln number of lines per ?eld (lower 8 of 10 bits) 028c 0 to 7 nrpx_div4 number of pixels per line divided-by-4 028d 0 transparent_mode bypass panoramic zoom: 0 = panoramic zoom active, 1 = bypass 1 c0 (msb) linear compression or expansion value (msb) 2 to 3 nrln (msbs) number of lines per ?eld (higher 2 of 10 bits) 4to7 - reserved host address 0280h to 0284h and 0290h (mid-end control) 0280 0 to 7 mid_hstart bandwidth detection window horizontal start (lower 8 of 10 bits) 0281 0 to 7 bw_hstop bandwidth detection window horizontal stop (lower 8 of 10 bits) 0282 0 to 7 bw_hstart bandwidth detection window vertical start (lower 8 of 10 bits) 0283 0 to 7 bw_hstop bandwidth detection window vertical stop (lower 8 of 10 bits) 0284 0 to 1 bw_hstart (msbs) bandwidth detection window horizontal start (higher 2 of 10 bits) 2 to 3 bw_hstop (msbs) bandwidth detection window horizontal stop (higher 2 of 10 bits) 4 to 5 bw_hstart (msbs) bandwidth detection window vertical start (higher 2 of 10 bits) 6 to 7 bw_hstop (msbs) bandwidth detection window vertical stop (higher 2 of 10 bits) 0290 0 bypass_downsampling bypass downsampling: 0 = downsampling active, 1 = bypass 1 mid_uv_inv inverts uvo output signals: 0 = no inversion, 1 = inversion 2 bypass_fsrc bypass fixed sample rate converter (fsrc): 0 = fsrc active, 1 = bypass 3to7 - reserved host address 0298h to 029fh (back-end control) 0298 0 to 7 be_hstart back-end window horizontal start (lower 8 of 10 bits) 0299 0 to 7 be_hstop back-end window horizontal stop (lower 8 of 10 bits) 029a 0 to 7 be_hstart back-end window vertical start (lower 8 of 10 bits) 029b 0 to 7 be_hstop back-end window vertical stop (lower 8 of 10 bits) host address (hex) bit name description
2002 may 28 27 philips semiconductors product speci?cation sample rate converter with embedded high quality dynamic noise reduction and expansion port SAA4979h 029c 0 to 1 be_hstart (msbs) back-end window horizontal start (higher 2 of 10 bits) 2 to 3 be_hstop (msbs) back-end window horizontal stop (higher 2 of 10 bits) 4 to 5 be_hstart (msbs) back-end window vertical start (higher 2 of 10 bits) 6 to 7 be_hstop (msbs) back-end window vertical stop (higher 2 of 10 bits) 029d 0 to 7 exp_hstart expansion port input window: horizontal start (lower 8 of 10 bits) 029e 0 to 1 exp_hstart (msbs) expansion port input window: horizontal start (higher 2 of 10 bits) 2to7 - reserved 029f 0 bypass_upsampling bypass upsampling: 0 = upsampling active, 1 = bypass 1 extern_device external device multiplexer: 0 = internal, 1 = data from external device 2to7 - reserved host address 02a0h to 02a6h (dynamic horizontal smart peaking) 02a0 0 to 7 steepness_vstart steepness detection window vertical start; 4 lines resolution 02a1 0 to 7 steepness_vstop steepness detection window vertical stop; 4 lines resolution 02a2 0 to 7 steepness_hstart steepness detection window horizontal start; 4 pixels resolution 02a3 0 to 7 steepness_hstop steepness detection window horizontal stop; 4 pixels resolution 02a4 0 to 2 pk_alpha peaking a : 1 16 (0, 1, 2, 3, 4, 5, 6, 8) 3 to 5 pk_beta peaking b : 1 16 (0, 1, 2, 3, 4, 5, 6, 8) 6 and 7 - reserved 02a5 0 to 2 pk_tau peaking t : 1 16 (0, 1, 2, 3, 4, 5, 6, 8) 3 and 4 pk_delta peaking amplitude dependent attenuation: 1 4 (0, 1, 2, 4) 5 and 6 pk_neggain peaking attenuation of undershoots: 1 4 (0, 1, 2, 4) 7 - reserved 02a6 0 to 3 pk_corthr peaking coring threshold: 0, 4, 8, 12 , 16 to 60 lsb 4 output_range output range: output range = 0: 9 bits for the nominal output signal, black level: 288 and white level: 727; output range = 1: 10 bits for the nominal output signal, black level: 64 and white level: 940 5to7 - reserved host address 02a8h and 02a9h (dcti) 02a8 0 to 2 dcti_gain dcti gain: 0, 1, 2, 3, 4, 5, 6 and 7 3 to 6 dcti_threshold dcti threshold: 0, 1 to 15 7 dcti_ddx_sel dcti selection of ?rst differentiating ?lter; see fig.9 02a9 0 and 1 dcti_limit dcti limit for pixel shift range: 0, 1, 2 and 3 2 dcti_separate dcti separate processing of u and v signals; 0 = off; 1 = on 3 dcti_protection dcti over the hill protection; 0 = off; 1 = on 4 dcti_?lteron dcti post-?lter; 0 = off; 1 = on 5 dcti_superhill dcti super hill mode; 0 = off; 1 = on 6 and 7 - reserved host address (hex) bit name description
2002 may 28 28 philips semiconductors product speci?cation sample rate converter with embedded high quality dynamic noise reduction and expansion port SAA4979h host address 02b0h to 02bbh and 02aah (post processing) 02b0 0 to 3 sidepanel_u side panel colour u value (4 msb) 4 to 7 sidepanel_v side panel colour v value (4 msb) 02b1 0 to 7 sidepanel_y side panel luminance value (8 msb) 02b2 0 to 7 sidepanel_hstart side panel start position (higher 8 of 10 bits) 02b3 0 to 7 sidepanel_hstop side panel stop position (higher 8 of 10 bits) 02b4 0 to 3 y_delay y delay relative to uv channel, in clock cycles: - 8, - 7, - 6, - 5, - 4, - 3, - 2, - 1, 0, 1, 2, 3, 4, 5, 6, and 7 4 uv_inv_out inverts uv output signals: 0 = no inversion, 1 = inversion 5 y_dac_current gain y digital-to-analog converter: 0 = 2 m a/bit (range 1), 1=4 m a/bit (range 0); see fig.6 6to7 - reserved 02b5 0 to 7 bln_hstart blanking window horizontal start position (lower 8 of 10 bits) 02b6 0 to 7 bln_hstop blanking window horizontal stop position (lower 8 of 10 bits) 02b7 0 to 7 bln_vstart blanking window vertical start position (lower 8 of 10 bits) 02b8 0 to 7 bln_vstop blanking window vertical stop position (lower 8 of 10 bits) 02b9 0 to 1 bln_hstart (msbs) blanking window horizontal start position (higher 2 of 10 bits) 2 to 3 bln_hstop (msbs) blanking window horizontal stop position (higher 2 of 10 bits) 4 to 5 bln_vstart (msbs) blanking window vertical start position (higher 2 of 10 bits) 6 to 7 bln_vstop (msbs) blanking window vertical stop position (higher 2 of 10 bits) 02ba 0 to 1 nlp_u non-linear phase ?lter settings m : (0, 1 4 , 1 2 , 1 2 ) 2 to 3 nlp_l non-linear phase ?lter settings l : (0, 1 8 , 2 8 , 3 8 ) 4 to 5 sidepanel_hstart (lsbs) side panel start position (lower 2 of 10 bits) 6 to 7 sidepanel_hstop (lsbs) side panel stop position (lower 2 of 10 bits) 02bb 0 to 7 pip_frame_hstart pip frame: horizontal start position (lower 8 of 10 bits) 02bc 0 to 7 pip_frame_hstop pip frame: horizontal stop position (lower 8 of 10 bits) 02bd 0 to 7 pip_frame_vstart pip frame: vertical start position (lower 8 of 10 bits) 02be 0 to 7 pip_frame_vstop pip frame: vertical stop position (lower 8 of 10 bits) 02bf 0 to 1 pip_frame_vstart (msbs) pip frame: vertical start position (higher 2 of 10 bits) 2 to 3 pip_frame_vstop (msbs) pip frame: vertical stop position (higher 2 of 10 bits) 4 to 5 pip_frame_hstart (msbs) pip frame: horizontal start position (higher 2 of 10 bits) 6 to 7 pip_frame_hstop (msbs) pip frame: horizontal stop position (higher 2 of 10 bits) 02aa 0 to 3 pip_frame_width (msbs) pip horizontal frame width (0 to 15 pixel) 4 to 7 pip_frame_height (msbs) pip vertical frame width (0 to 15 pixel) host address (hex) bit name description
2002 may 28 29 philips semiconductors product speci?cation sample rate converter with embedded high quality dynamic noise reduction and expansion port SAA4979h table 8 read register at 1f h host address 0300h to 0305h (pll) 0300 0 to 2 pll_cd_value damping factor 3 to 7 pll_ck_value time constant 0301 0 to 1 - reserved 2 to 4 pll_idto (msbs) signed increment offset of dto (msbs) 5 0 to be cleared 6 pll_off_hif freeze frequency 7 pll_open disable outer loop: 0 = outer loop closed, 1 = outer loop open 0302 0 to 7 pll_idto2 signed increment offset of dto (higher byte) 0303 0 to 7 pll_idto1 signed increment offset of dto (lower byte) 0304 0 pll_freq_shift operating frequency shift: 0 = no shift, 1 = frequency shift of 8% 1 pll_limiter_off pll frequency limiter of outer loop: 0 = limiter on, 1 = limiter off 2to7 - reserved 0305 0 to 2 pll_cd_adapt damping factor in adaptive mode 3 to 7 pll_ck_adapt time constant in adaptive mode host address (hex) bit name description host address 0142h and 0143h (system control) 0142 0 to 7 ?eldinf result of ?eld length measurement (lower 8 of 10 bits) 0143 0 to 1 ?ledinf (msbs) result of ?eld length measurement (higher 2 of 10 bits) 2 frg ?eld recognition of incoming source 3to7 - reserved host address 01c0h to 01c4h (noise estimator) 01c0 0 to 3 nest noise estimation result 4to7 - reserved 01c1 0 to 7 nest_?lt noise estimation value ?ltered 01c2 0 to 7 detail_cnt_h output of detail counter, higher byte 01c3 0 to 7 detail_cnt_l output of detail counter, lower byte 01c4 0 to 7 grey_cnt output of grey counter host address 01cah and 01cbh (black bar detection) 01ca 0 to 6 bbd_1st_videoline line number of ?rst video line 7 bbd_last_videoline (msb) line number of last video line (msb) 01cb 0 to 7 bbd_last_videoline line number of last video line host address (hex) bit name description
2002 may 28 30 philips semiconductors product speci?cation sample rate converter with embedded high quality dynamic noise reduction and expansion port SAA4979h table 9 read register at 2f h 8.2 special function registers (sfrs) table 10 snert-bus control host address (hex) bit name description host address 0242h (system control) 0242 0 to 3 dsp?ds number of display ?elds - 1 4 dsp_unlock display unlock: 0 = normal operation, 1 = vertical display timing unlocked 5to7 - reserved host address 02c8h (uv bandwidth detection) 02c8 0 to 7 uv_bw_detect result of uv bandwidth detection (unsigned value) host address 02d0h (dynamic peaking) 02d0 0 to 7 steepness_max result of steepness detection (unsigned value) sfr address (hex) bit read/write name description special function register 9ah (sncon); reset value: 00h 9a 0 read trm snert transmit busy ?ag: trm is set to logic 1 after sfr 9ch (snwda) is accessed, after a transmission trm is set to logic 0 1 read and write rec snert receive busy ?ag: if rec is set to logic 1 the contents of sfr 9bh (snadd) is transmitted, after reception is completed rec is set to logic 0 2to6 -- reserved 7 read and write mb2 snert baud rate: 0 = 1 mhz, 1 = 2 mhz special function register 9bh (snadd) 9b 0 to 7 write snadd snert address special function register 9ch (snwda) 9c 0 to 7 write snwda snert data to be transmitted special function register 9dh (snrda) 9d 0 to 7 read snrda data received from snert-bus
2002 may 28 31 philips semiconductors product speci?cation sample rate converter with embedded high quality dynamic noise reduction and expansion port SAA4979h table 11 power control 9 limiting values in accordance with the absolute maximum rating system (iec 60134). notes 1. machine model class b, equivalent to discharging a 200 pf capacitor through a 0 w series resistor (0 w is actually 0.75 m h+10 w ). 2. human body model class b, equivalent to discharging a 100 pf capacitor through a 1500 w series resistor. sfr address (hex) bit read/write name description special function register 87h (pcon); reset value: 00h 87 0 read and write idl idle mode bit: 0 = normal operation, 1 = idle mode operation 1 read and write pd power-down bit: 0 = normal operation, 1 = power-down mode 2to3 -- reserved 4 read and write wle watchdog load enable: 0 = loading of watchdog timer disabled, 1 = loading of watchdog timer enabled ew enable watchdog: 0 = watchdog disabled, 1 = watchdog enabled; once this bit is set only a synchronous reset can clear it 5 read and write rfi radio frequency interference bit: disables toggling of internal ale signal during on-chip program access if set to logic 1 6 read and write ard auxiliary ram disable: setting this bit will force movx instructions to access off-chip memory instead of auxram 7 -- reserved symbol parameter conditions min. max. unit v ddd digital supply voltage - 0.5 +4.0 v v dda analog supply voltage - 0.5 +4.0 v v ddi internal i/o supply voltage - 0.5 +4.0 v v ddo i/o supply voltage v ddd = 3.3 v - 0.5 +3.8 v v ddp supply voltage for protection circuits - 0.5 +5.5 v v i input voltage for all digital input pins v ddp =5v - 0.5 +5.5 v v ddp = 3.3 v - 0.5 +3.8 v v i input voltage for all digital i/o pins - 0.5 +3.8 v i dd(tot) total supply current - 300 ma i o short circuit output current - 30 ma p tot total power dissipation - 1.2 w t stg storage temperature - 25 +150 c t j junction temperature 0 +125 c t amb ambient temperature 0 +70 c v es electrostatic handling voltage note 1 - 200 + 200 v note 2 - 2000 + 2000 v
2002 may 28 32 philips semiconductors product speci?cation sample rate converter with embedded high quality dynamic noise reduction and expansion port SAA4979h 10 thermal characteristics 11 characteristics v ddd = 3.0 to 3.6 v; v ddo = 3.0 to 3.6 v; v dda = 3.15 to 3.45 v; t amb =0to70 c; unless otherwise speci?ed. symbol parameter conditions value unit r th(j-a) thermal resistance from junction to ambient in free air 45 k/w symbol parameter conditions min. typ. max. unit supplies v ddd digital supply voltage 3.0 3.3 3.6 v v dda analog supply voltage 3.15 3.30 3.45 v v ddi internal i/o supply voltage 3.0 3.3 3.6 v v ddo i/o supply voltage 3.0 3.3 3.6 v v ddp protection supply voltage 3.0 5.0 5.5 v i ddd digital supply current - 120 160 ma i dda analog supply current - 40 50 ma i ddi internal i/o supply current - 02 ma i ddo i/o supply current - 10 40 ma i ddp protection supply current - 01 ma output transfer function (sample rate 32 mhz/10 bits) inl integral non linearity - 2 - +2 lsb dnl differential non linearity - 1 - +1 lsb luminance output signal: pin yout v o(p-p) y output level (peak-to-peak value) output range = 0: nominal amplitude digital 288 to 727; output range = 1: nominal amplitude digital 64 to 940 0.94 1.00 1.06 v v o(black) y black level (voltage at 288) output range = 0 0.837 0.891 0.944 v y black level (voltage at 64) output range = 1 0.836 0.889 0.942 v r o output resistance - 75 85 w c l capacitive load -- 25 pf s/n signal-to-noise ratio nominal amplitude; 0 to 10 mhz 46 -- db colour difference output signals: pins uout and vout v o(p-p) u output level (peak-to-peak value) for saturated colour bar with 75% of maximum amplitude 1.25 1.33 1.41 v v output level (peak-to-peak value) for saturated colour bar with 75% of maximum amplitude 0.99 1.05 1.11 v
2002 may 28 33 philips semiconductors product speci?cation sample rate converter with embedded high quality dynamic noise reduction and expansion port SAA4979h v o(colourless) u colourless level (voltage at 512) 1.32 1.40 1.48 v v colourless level (voltage at 512) 1.32 1.40 1.48 v g d(u-v) gain matching u to v - 13 % r o output resistance - 75 85 w c l capacitive load -- 25 pf s/n signal-to-noise ratio nominal amplitude; 0 to 10 mhz 46 -- db digital output signals: pins oie2, rstr2 and re2 v oh high-level output voltage i oh = - 0.5 ma 2.4 -- v v ol low-level output voltage i ol = 0.5 ma -- 0.4 v digital output signals: all pins except oie2, rstr2 and re2 v oh high-level output voltage i oh = - 2.0 ma 2.4 -- v v ol low-level output voltage i ol = 2.0 ma -- 0.4 v digital input signals: pins di1, di2, llc1, llc2, rstw2, tdi, tms,tck, bce and trst v ih high-level input voltage 2 - v ddp + 0.3 v v il low-level input voltage -- 0.8 v i li input leakage current -- 10 m a digital input signals: pins uvi, yi, rei and rst v ih high-level input voltage 2.0 - 5.5 v v il low-level input voltage -- 0.8 v i ih high-level input current -- 100 m a i il low-level input current -- 10 m a digital input signal: pin clkext v ih high-level input voltage 2.0 - 5.5 v v il low-level input voltage -- 0.8 v i li input leakage current -- 10 m a digital input/output signals: pins snrst and p1.2 to p1.5 v oh high-level output voltage i oh = - 2.0 ma 2.4 -- v v ol low-level output voltage i ol = 2.0 ma 0 - 0.4 v v ih high-level input voltage 2.0 - 3.8 v v il low-level input voltage 0 - 0.8 v i ih high-level input current -- 10 m a i il low-level input current -- 100 m a digital input/output signal: pin snda v oh high-level output voltage i oh = - 2.0 ma 2.4 -- v v ol low-level output voltage i ol = 2.0 ma 0 - 0.4 v v ih high-level input voltage 2.0 - 5.5 v v il low-level input voltage 0 - 0.8 v i li input leakage current -- 10 m a symbol parameter conditions min. typ. max. unit
2002 may 28 34 philips semiconductors product speci?cation sample rate converter with embedded high quality dynamic noise reduction and expansion port SAA4979h data output timing: pins oie2, rstr2 and re2 (c l = 15 pf); timing referenced to llc1 t d(o) output delay time see fig.8 -- 26 ns t h(o) output hold time see fig.8 4 -- ns data output timing: pins yo, uvo, ie, reo, ads, hd and vd (c l = 15 pf); timing referenced to clk32 t d(o) output delay time see fig.8 -- 20 ns t h(o) output hold time see fig.8 3 -- ns data input timing: pins rstw2, di1 and di2; timing referenced to llc1 t su(i) input set-up time see fig.8 4 -- ns t h(i) input hold time see fig.8 3 -- ns data input timing: pins yi, uvi and rei; timing referenced to clk32 t su(i) input set-up time see fig.8 4 -- ns t h(i) input hold time see fig.8 3 -- ns clock input timing: pins llc1 and llc2 t cy cycle time 34 37 40 ns d clk clock duty factor 40 50 60 % t r clock rise time see fig.8 -- 5ns t f clock fall time see fig.8 -- 5ns clock input timing: pin clkext t cy cycle time 29.00 31.25 34.00 ns d clk clock duty factor 40 50 60 % t r clock rise time see fig.8 -- 5ns t f clock fall time see fig.8 -- 5ns clock output timing: pin clk32 (c l =25pf) t cy cycle time 26.00 31.25 38.00 ns d clk clock duty factor 45 50 55 % t r output rise time see fig.8 -- 4ns t f output fall time see fig.8 -- 4ns pll function (base frequency 32 mhz) s line-line sigma value of line-to-line jitter locked to stable h signal - 0.4 1.0 ns i 2 c-bus signals: pins sda and scl; note 1 v ih high-level input voltage 0.7v ddo - 5.5 v v il low-level input voltage -- 0.3v ddo v v hys hysteresis voltage 0.05v ddo -- v v ol low-level output voltage i ol = 3.0 ma -- 0.4 v i li input leakage current -- 10 m a f scl scl clock frequency -- 400 khz t r rise time of sda and scl -- 0.3 m s t f fall time of sda and scl -- 0.3 m s symbol parameter conditions min. typ. max. unit
2002 may 28 35 philips semiconductors product speci?cation sample rate converter with embedded high quality dynamic noise reduction and expansion port SAA4979h notes 1. the ac characteristics are in accordance with the i 2 c-bus specification for fast mode (clock frequency maximum 400 khz). information about the i 2 c-bus can be found in the brochure i 2 c-bus and how to use it (order number 9398 393 40011). 2. more information about the snert-bus protocol can be found in application note the snert-bus specification (an95127). t hd;sta hold time start condition 0.6 -- m s t hd;dat data hold time 0 - 0.9 m s t low scl low time 1.3 -- m s t high scl high time 0.6 -- m s t su;dat data set-up time 100 -- ns t su;sta set-up time repeated start 0.6 -- m s t su;sto set-up time stop condition 0.6 -- m s t buf bus free time between a stop and start condition 1.3 -- m s snert-bus timing (valid for both 1 and 2 mbaud): pins snda and sncl; note 2 t su(i) input set-up time 80 -- ns t h(i) input hold time 0 -- ns t h(o) output hold time 50 -- ns t su(o) output set-up time 260 -- ns t cy(sncl) sncl cycle time 500 - 1000 ns t snrsth snrst pulse high time 500 -- ns t d(snrst-dat) delay snrst pulse to data 200 -- ns symbol parameter conditions min. typ. max. unit handbook, full pagewidth mhc203 clock 2.4 v 1.5 v 0.6 v 2.0 v 0.8 v 2.4 v 0.4 v input data output data t h(o) t d(o) t r t f t su(i) t h(i) fig.8 timing diagram.
2002 may 28 36 philips semiconductors product speci?cation sample rate converter with embedded high quality dynamic noise reduction and expansion port SAA4979h 12 transfer functions handbook, halfpage 0 0.25 1 0 0.2 mhc204 signal amplitude f/f s 0.4 0.6 0.8 0.05 0.1 0.15 0.2 (2) (1) fig.9 dcti first differentiating filter; transfer function with variation of control signal dcti_ddx_sel. (1) dcti_ddx_sel = 1. (2) dcti_ddx_sel = 0. handbook, full pagewidth mhc205 digital signal amplitude samples (1) (5) (4) (3) (2) 500 - 100 - 200 300 400 - 300 200 - 400 100 0 - 500 fig.10 dcti with variation of gain setting (limit = 1). (1) input signal. (2) gain = 1. (3) gain = 3. (4) gain = 5. (5) gain = 7.
2002 may 28 37 philips semiconductors product speci?cation sample rate converter with embedded high quality dynamic noise reduction and expansion port SAA4979h handbook, full pagewidth mhc206 digital signal amplitude samples (1) (4) (3) (2) 500 - 100 - 200 300 400 - 300 200 - 400 100 0 - 500 fig.11 dcti with variation of limit setting (gain = 7). (1) input signal. (2) limit = 1. (3) limit = 2. (4) limit = 3. handbook, halfpage 0 0.5 1.2 0 0.4 0.8 mhc207 0.1 0.2 0.3 0.4 signal amplitude f/f s fig.12 dcti post-filter transfer function.
2002 may 28 38 philips semiconductors product speci?cation sample rate converter with embedded high quality dynamic noise reduction and expansion port SAA4979h handbook, full pagewidth 0.5 10 0 f/f s signal amplitude (db) 0 0.1 0.2 0.3 0.4 2 4 6 8 mhc208 (7) (6) (5) (4) (3) (2) (1) fig.13 transfer function of the peaking high-pass filter with variation of b ( a =0; t = 0). (1) b = 1 16 . (2) b = 2 16 . (3) b = 3 16 . (4) b = 4 16 . (5) b = 5 16 . (6) b = 6 16 . (7) b = 8 16 .
2002 may 28 39 philips semiconductors product speci?cation sample rate converter with embedded high quality dynamic noise reduction and expansion port SAA4979h handbook, full pagewidth 0.5 10 0 f/f s signal amplitude (db) 0 0.1 0.2 0.3 0.4 2 4 6 8 mhc209 (7) (6) (5) (4) (3) (2) (1) fig.14 transfer function of the peaking band-pass with variation of a ( b =0; t = 0). (1) a = 1 16 . (2) a = 2 16 . (3) a = 3 16 . (4) a = 4 16 . (5) a = 5 16 . (6) a = 6 16 . (7) a = 8 16 .
2002 may 28 40 philips semiconductors product speci?cation sample rate converter with embedded high quality dynamic noise reduction and expansion port SAA4979h handbook, full pagewidth 0.5 10 0 f/f s signal amplitude (db) 0 0.1 0.2 0.3 0.4 2 4 6 8 mhc210 (7) (6) (5) (4) (3) (2) (1) fig.15 transfer function of peaking low band-pass with variation of t ( a =0; b = 0). (1) t = 1 16 . (2) t = 2 16 . (3) t = 3 16 . (4) t = 4 16 . (5) t = 5 16 . (6) t = 6 16 . (7) t = 8 16 . handbook, halfpage mhc193 cor_thr - cor_thr input output fig.16 peaking coring function.
2002 may 28 41 philips semiconductors product speci?cation sample rate converter with embedded high quality dynamic noise reduction and expansion port SAA4979h 13 application information the SAA4979h supports different scan-rate upconversion concepts. the simple one is illustrated in fig.17. in this application no further components are needed for a 100 hz conversion based on a field repetition algorithm (aabb mode). the system can be upgraded by a vector based motion estimation and compensation function. in this case the saa4992h together with two field memories (saa4955) are needed (see figs 18 and 19 respectively). in addition the SAA4979h supports field based and frame based picture-in-picture applications. to realize the full performance frame based pip function a second video decoder (saa7118) and two additional field memories are required (see fig.20).
2002 may 28 42 philips semiconductors product speci?cation sample rate converter with embedded high quality dynamic noise reduction and expansion port SAA4979h handbook, full pagewidth mhc194 8.2 k w 10 m f + 3.3 v + 3.3 v + 3.3 v + 3.3 v n.c. n.c. n.c. n.c. n.c. n.c. n.c. rei reo clk32 SAA4979h low pass low pass n.c. ie n.c. snrst n.c. sncl n.c. snda low pass saa7118 video decoder 24.576 mhz fsw main rgb main yuv main yc main cvbs main yc r c b itu 656 llc1 llc2 oie2 re2 rstr2 trst tdo sda scl vd hd 8 16 n.c. 16 16 112 111 42 12 pf 18 pf 34 to 41, 51, 60 62 81 65 to 80 43 44 46 48 45, 49, 50, 56 54 55 58 59 tms 32 tdi 31 tck 30 33 bce 128 28 4 3 2 7 to 14 rstw2 rst 8 6 19 to 26 84 108 85 to 88, 90 to 93, 95 to 98, 100 to 103 107 110 83 + 3.3 v + 3.3 v n.c. 18 106, 113 to 116, 119 to 127 + 3.3 v 5, 15, 27 1, 17, 29 + 3.3 v 64, 89, 99, 117 + 3.3 v 61, 105 53, 82, 94, 109 63, 104 118 + 3.3 v 12 mhz 47, 52, 57 fig.17 application diagram 1.
2002 may 28 43 philips semiconductors product speci?cation sample rate converter with embedded high quality dynamic noise reduction and expansion port SAA4979h handbook, full pagewidth mhc195 8.2 k w 10 m f + 3.3 v + 3.3 v + 3.3 v + 3.3 v n.c. n.c. rei SAA4979h saa7118 video decoder low pass low pass low pass pip module 24.576 mhz fsw pip rgb pip yuv pip yc pip cvbs pip yc r c b itu 656 llc1 llc1 oie2 re2 rstr2 trst tdo sda scl 8 16 16 112 111 42 34 to 41, 51, 60 62 hd vd 81 65 to 80 43 44 46 48 45, 49, 50, 56 54 55 58 59 tms 32 tdi 31 tck 30 33 bce 128 28 4 3 2 7 to 14 yc r c b itu 656 rstw2 rst 8 6 19 to 26 i j g 84 f 108 85 to 88, 90 to 93, 95 to 98, 100 to 103 d 107 c 110 b 83 a h e + 3.3 v + 3.3 v n.c. 18 106, 113 to 116, 119 to 127 + 3.3 v 5, 15, 27 1, 17, 29 + 3.3 v 64, 89, 99, 117 + 3.3 v 61, 105 53, 82, 94, 109 63, 104 118 + 3.3 v 12 mhz 47, 52, 57 12 pf 18 pf fig.18 application diagram 2 (continued in fig.19).
2002 may 28 44 philips semiconductors product speci?cation sample rate converter with embedded high quality dynamic noise reduction and expansion port SAA4979h handbook, full pagewidth mhc196 16 17, 23, 55, 58, 80, 100, 104, 137, 143 1, 15, 28, 36, 54, 59, 78, 81, 99, 105, 120, 121, 135, 145 24, 29, 30 25 27 26 37 to 52 60 53 61 to 68, 70 to 77 79 saa4955tj clk32 clk32 saa4992h j i g f d c b a e h + 3.3 v + 3.3 v + 3.3 v n.c. trst tdo 35 tms 33 tdi 32 tck 31 34 + 3.3 v 20 + 3.3 v 19, 22 + 3.3 v 20, 21 + 3.3 v 19 2 to 13 14 3 to 14 27 to 38 24 26 vd 25 23 15 vd 16 ie 18 17 12 12 1, 2, 39, 40 146 136, 139, 140, 144 134 n.c. 147 to 152, 154 to 159 122 to 133 + 3.3 v 16, 21, 69, 90, 102, 113, 141, 153, 160 + 3.3 v + 3.3 v saa4955tj clk32 clk32 clk32 snrst sncl snda reo + 3.3 v 19, 22 + 3.3 v 20, 21 3 to 14 27 to 38 24 26 vd 25 23 15 vd 16 ie 18 17 12 12 12 1, 2, 39, 40 106 107 to 112, 114 to 119 82 to 89, 91 to 98 n.c. + 3.3 v 18, 22, 56, 57, 101, 103, 138, 142 fig.19 application diagram 3 (continued from fig.18).
2002 may 28 45 philips semiconductors product speci?cation sample rate converter with embedded high quality dynamic noise reduction and expansion port SAA4979h 2002 may 28 45 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... n dbook, full pagewidth mhc197 saa7118 video decoder 24.576 mhz fsw pip rgb pip yuv pip yc pip cvbs pip we2 rstw2 sda scl 11 10 20 1 2 to 9 12 to 19 swck2 rstw2 swck2 8 74f574 + 3.3 v saa4955tj llc1 rstr2 re2 oie2 + 3.3 v 19, 22 + 3.3 v 20, 21 7 to 14 3 to 6 35 to 38 27 to 34 26 25 24 23 15 16 17 18 8 1, 2, 39, 40 n.c. we2 ie2 rstw2 swck2 saa4955tj + 3.3 v 19, 22 + 3.3 v 20, 21 7 to 14 3 to 6 35 to 38 27 to 34 26 25 24 23 15 16 17 18 8 1, 2, 39, 40 n.c. yc r c b itu 656 8 fig.20 pip module.
2002 may 28 46 philips semiconductors product speci?cation sample rate converter with embedded high quality dynamic noise reduction and expansion port SAA4979h handbook, halfpage mhc198 240 w 2.7 m h 8.2 pf 15 pf v in v out 68 pf fig.21 low-pass filter. handbook, full pagewidth mhc199 5.1 k w 240 w 100 w bc846 bc856 10 m f v in + 8 v + 8 v + 8 v 200 w 200 w 240 w 2.7 k w 240 w 4.7 m h 4.7 pf 39 pf v out 39 pf fig.22 low-pass filter with termination.
2002 may 28 47 philips semiconductors product speci?cation sample rate converter with embedded high quality dynamic noise reduction and expansion port SAA4979h 14 package outline unit a 1 a 2 a 3 b p ce (1) (1) (1) eh e ll p z y w v q references outline version european projection issue date iec jedec eiaj mm 0.50 0.25 3.70 3.15 0.25 0.45 0.30 0.23 0.13 28.1 27.9 0.8 1.8 1.4 7 0 o o 0.2 0.3 0.1 1.6 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 1.03 0.73 sot320-2 134e13 ms-022 99-12-27 00-01-19 d (1) 28.1 27.9 h d 31.45 30.95 31.45 30.95 e z 1.8 1.4 d 0 5 10 mm scale pin 1 index b p e q e a 1 a l p detail x l (a ) 3 b 32 c b p e h a 2 d h v m b d z d a z e e v m a x 1 128 97 96 65 64 33 y w m w m 128 leads (lead length 1.6 mm); body 28 x 28 x 3.4 mm; high stand-off height qfp128: plastic quad flat package; sot320-2 a max. 4.07
2002 may 28 48 philips semiconductors product speci?cation sample rate converter with embedded high quality dynamic noise reduction and expansion port SAA4979h 15 soldering 15.1 introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering can still be used for certain surface mount ics, but it is not suitable for fine pitch smds. in these situations reflow soldering is recommended. 15.2 re?ow soldering reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical reflow peak temperatures range from 215 to 250 c. the top-surface temperature of the packages should preferable be kept below 220 c for thick/large packages, and below 235 c for small/thin packages. 15.3 wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was specifically developed. if wave soldering is used the following conditions must be observed for optimal results: use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 15.4 manual soldering fix the component by first soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
2002 may 28 49 philips semiconductors product speci?cation sample rate converter with embedded high quality dynamic noise reduction and expansion port SAA4979h 15.5 suitability of surface mount ic packages for wave and re?ow soldering methods notes 1. for more detailed information on the bga packages refer to the (lf)bga application note (an01026); order a copy from your philips semiconductors sales office. 2. all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . 3. these packages are not suitable for wave soldering. on versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. on versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 4. if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. 5. wave soldering is suitable for lqfp, tqfp and qfp packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 6. wave soldering is suitable for ssop and tssop packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. package (1) soldering method wave reflow (2) bga, lbga, lfbga, sqfp, tfbga, vfbga not suitable suitable hbcc, hbga, hlqfp, hsqfp, hsop, htqfp, htssop, hvqfn, hvson, sms not suitable (3) suitable plcc (4) , so, soj suitable suitable lqfp, qfp, tqfp not recommended (4)(5) suitable ssop, tssop, vso not recommended (6) suitable
2002 may 28 50 philips semiconductors product speci?cation sample rate converter with embedded high quality dynamic noise reduction and expansion port SAA4979h 16 data sheet status notes 1. please consult the most recently issued data sheet before initiating or completing a design. 2. the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the latest information is available on the internet at url http://www.semiconductors.philips.com. data sheet status (1) product status (2) definitions objective data development this data sheet contains data from the objective specification for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. preliminary data quali?cation this data sheet contains data from the preliminary specification. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. product data production this data sheet contains data from the product specification. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. changes will be communicated according to the customer product/process change noti?cation (cpcn) procedure snw-sq-650a. 17 definitions short-form specification ? the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition ? limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affect device reliability. application information ? applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 18 disclaimers life support applications ? these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes ? philips semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
2002 may 28 51 philips semiconductors product speci?cation sample rate converter with embedded high quality dynamic noise reduction and expansion port SAA4979h 19 purchase of philips i 2 c components purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011.
? koninklijke philips electronics n.v. 2002 sca74 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. philips semiconductors C a worldwide company contact information for additional information please visit http://www.semiconductors.philips.com . fax: +31 40 27 24825 for sales of?ces addresses send e-mail to: sales.addresses@www.semiconductors.philips.com . printed in the netherlands 753504/01/pp 52 date of release: 2002 may 28 document order number: 9397 750 09561

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